devices.xylo.syns61201.cycles_model

devices.xylo.syns61201.cycles_model(config: XyloConfiguration, input_sp: float | ndarray | Tensor | array = 1.0, hidden_sp: float | ndarray | Tensor | array = 1.0, output_sp: float | ndarray | Tensor | array = 1.0) → Tuple[float, float][source]

Calculate the average number of cycles required for a given network architecture

This function contains a model which estimates the number of master clock cycles required for the Xylo SNN SYNS61202 inference core to compute one time-step for a given chip configuration in config. Use devices.xylo.syns61201.config_from_specification() to obtain a chip configuration, along with Module.as_graph() and devices.xylo.syns61201.mapper(), as described in the deployment tutorials for Xylo.

By default the model provides a “worst-case” estimation, assuming that every neuron and every input channel fire on each time-step. If desired, real input rasters and real hidden and output spike rasters can be provided for analysis. Alternative spiking probabilities can also be provided as floats 0..1.

Note that when estimating spiking probablility, only boolean values are relevant — either a spike or no spike per time step per channel. Multiple events per bin cost the same as a single event.

Parameters:

  • config (XyloA2Config) – A XyloAudio 2 configuration for which to calculate the cycle requirements

  • input_sp (FloatVector) – Either a floating-point number 0..1, specifying the average input firing rate, or an actual input spike raster to use in evaluation. Default: 1.0; estimate a worst-case scenario

  • hidden_sp (FloatVector) – Either a floating-point number 0..1, specifying the average hidden neuron firing rate, or an actual hidden spike raster to use in evaluation. Default: 1.0; estimate a worst-case scenario

  • output_sp (FloatVector) – Either a floating-point number 0..1, specifying the average output neuron firing rate, or an actual output spike raster to use in evaluation. Default: 1.0; estimate a worst-case scenario

Returns:

(clk_cyles_reqd, additional_isyn2_ops) clk_cyles_reqd (float): The average number of master clock cycles required for this configuration, for the Xylo SNN core to compute one network dt additional_isyn2_ops (float): The average additional number of operations required when Isyn2 is enabled. Will be zero if Isyn2 is disabled. Note: These operations occur in parallel to Isyn1, and do not require additional master clock cycles.

Return type:

Tuple[float, float]